`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    21:51:20 03/05/2013 
// Design Name: 
// Module Name:    tff 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module tff(
    input toggle,
    input clk,
    input reset_b,
    output t_out
    );
	 
	 //------------Signal Declarations/Internal Variables--------
reg temp_reg_i; // One clock shifted signal

//-------------Code Starts Here---------
always @ (posedge clk or negedge reset_b) begin
	if (reset_b == 1'b0)
		temp_reg_i <= 1'b0;
	else if (toggle == 1'b1)
		temp_reg_i <= !temp_reg_i;
end
assign t_out = temp_reg_i;


endmodule
